Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability

testability standard in the industry. Although its mandatory provisions focus narrowly on boardlevel assembly verification testing, primarily via the boundary-scan register, its test access port (TAP) and many optional provisions make the standard usable for a much broader range of applications. Since its inception, numerous extensions and applications have been proposed that allow the standard’s TAP to be used at the system level for general system-level test and maintenance tasks2,3 and at the chip level for accessing chip-level testability features. Chiplevel applications thus far have used the port for accessing the chip’s scan design4,5 or for simple triggering of on-chip built-in self-test features via the RUNBIST instruction.6 Applications requiring general access to chipwide testability features that operate at the full chip-clock rate have been rare, primarily because of one of the standard’s basic tenets—namely, its dedicated test clock. The standard’s TAP uses its own dedicated test clock (tck_h) for a good reason: The clock ascertains the interoperability of components designed to operate with different clock speeds in different clock domains. While this maintains the integrity of board/system-level testability access, it limits the scope of the test features accessed to either those that already work with the test clock (such as the boundary-scan register) or those that are specially designed to work with the normal chip clock during normal operation and with the external test clock during test operation. Figure 1 shows one such frequently used scheme. The multiplexer used on the chip clock impacts the design of the entire chip logic, including internal testability features. The cost and complexity of designing this dual operation may be acceptable for features that provide value in the system environment, but they may be hard to justify for features that are used exclusively in the chip manufacturing environment and have no value at the board or system level. This article presents a method that enhances the test port to let it operate with two clocks: the standard-compliant external test clock and an alternative internal clock running synchronous to the chip clock. The former is used while accessing IEEE 1149.1-compliant features; the Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability Chip-Level Testability